Publication 

M. Chae=, S. Jang=, C. Hwang, H. Park, and J. Choi*, "A 65fsrms-Jitter and −272dB-FoMjitter,N 10.1GHz Fractional-N Digital PLL with a Quantization-Error-Compensating BBPD and an Orthogonal-Polynomial LMS Calibration," IEEE International Solid-State Circuits Conference (ISSCC), Accepted. (= Equally-Credited Authors)

S. Jang=, M. Chae=, H. Park, C. Hwang, and J. Choi*, "A Low-Jitter and Compact-Area Fractional-N Digital PLL with Fast Multi-Variable Calibration Using the Recursive Least Squares Algorithm," IEEE J. Solid-State Circuits (JSSC), Dec. 2024. (= Equally-Credited Authors)

S. Jang=, M. Chae=, H. Park=, C. Hwang, and J. Choi*, "A 5.5μs-Calibration-Time, Low-Jitter and Compact-Area Fractional-N Digital PLL Using the Recursive Least Squares (RLS) Algorithm," IEEE International Solid-State Circuits Conference (ISSCC), Feb. 2024.

Y. Jo, J. Kim, Y. Shin, H. Park, C. Hwang, Y. Lim, and J. Choi*, "A Wideband LO Generator for 5G FR1 Bands Using a Single LC-VCO-Based Subsampling PLL and a Ring-VCO-Based Fractional-Resolution Frequency Multiplier," IEEE J. Solid-State Circuits (JSSC), Early Access.

Y. Jo=, J. Kim=, Y. Shin, C. Hwang, H. Park, and J. Choi*, "A 135fsrms-Jitter 0.6−7.7GHz LO Generator Using a Single LC-VCO-Based Subsampling PLL and a Ring-Oscillator-Based Sub-Integer-N Frequency Multiplier", IEEE International Solid-State Circuits Conference (ISSCC), Feb. 2023. (= Equally-Credited Authors)

H. Park=, C. Hwang=, T. Seong, J. Choi*, "A Low-Jitter Ring-DCO-Based Fractional-N Digital PLL with a 1/8 DTC-Range-Reduction Technique Using a Quadruple-Timing-Margin Phase Selector," IEEE J. Solid-State Circuits (JSSC), Dec. 2022. (= Equally-Credited Authors)

C. Hwang=, H. Park=, Y. Lee, T. Seong, J. Choi*, "A Low-Jitter and Low-Fractional-Spur Ring-DCO-Based Fractional-N Digital PLL Using a DTC’s Second/Third-Order Nonlinearity Cancellation and a Probability-Density-Shaping ΔΣM,"  IEEE J. Solid-State Circuits (JSSC), Sep. 2022. (= Equally-Credited Authors)

C. Hwang=, H. Park=, T. Seong, J. Choi*, "A 188fsrms-Jitter and –243dB-FoMjitter 5.2GHz-Ring-DCO-Based Fractional-N Digital PLL with a 1/8 DTC-Range Reduction Technique Using a Quadruple-Timing-Margin Phase Selector," IEEE International Solid-State Circuits Conference (ISSCC), Feb. 2022. (= Equally-Credited Authors)

H. Park=, C. Hwang=, T. Seong=, Y. Lee, J. Choi*, "A 365fsRMS Jitter and −63dBc-Fractional Spur, 5.3GHz-Ring-DCO-Based Fractional-N DPLL Using a DTC’s Second/Third-Order Nonlinearity Cancellation and a Probability-Density-Shaping ΔΣM," IEEE International Solid-State Circuits Conference (ISSCC), Feb. 2021. (= Equally-Credited Authors)

S. Yoo=, S. Park=, S. Choi=, Y. Cho, H. Yoon, C. Hwang, J. Choi*, "An 82fsRMS-Jitter and 22.5mW-Power, 102GHz W-Band PLL Using a Power-Gating Injection-Locked Frequency Multiplier-Based Phase Detector in 65nm CMOS," IEEE International Solid-State Circuits Conference (ISSCC), Feb. 2021. (= Equally-Credited Authors)

Y. Lee=, T. Seong=, J. Lee, C. Hwang, H. Park, and J. Choi*, "A -240dB-FOMJIT and -115dBc/Hz-100kHz-PN, 7.7GHz-Ring-DCO-Based Digital PLL Using ...," IEEE International Solid-State Circuits Conference (ISSCC), accepted for presentation, Feb. 2020. (= Equally-Credited Authors)

T. Seong=, Y. Lee=, C. Hwang, J. Lee, H. Park, K. Lee, and J. Choi*, "A -58dBc-Worst Fractional Spur and -234dB-FOMJIT, 5.5GHz-Ring-DCO-Based Fractional-N DPLL Using ...," IEEE International Solid-State Circuits Conference (ISSCC), accepted for presentation, Feb. 2020. (= Equally-Credited Authors)

S. Park, J. Kim, C. Hwang, H. Park, S. Yoo, T. Seong, and J. Choi*, "A 0.1-1.5 GHz Wide Harmonic-Locking-Free Delay-Locked Loop Using an Exponential DAC", IEEE Microwave and Wireless Components Letters, Aug. 2019.

   Awards and Honors

2023-2024 SSCS Predoctoral Achievement Award Winner, Feb. 2024.

26th Samsung Humantech Paper Award, Silver Prize in Circuit Design, Feb. 2020.

27th Samsung Humantech Paper Award, Silver Prize in Circuit Design, Feb. 2021.

30th Samsung Humantech Paper Award, Bronze Prize in Circuit Design, Feb. 2024.

   Patents

J. Choi, H. Park, C. Hwang and T. Seong, Delta sigma modulator to prevent fractional-spur generation by loop non-linearity in fractional-N PLL, Application No.: 10-2021-0113993, Aug. 27, 2021. (Domestic, Filed)

J. Choi, Y. Lee, T. Seong, C. Hwang and H. Park, Low-flicker-noise digital phase-locked loop using a proportional- and integral-gain co-optimization, Application No.: 10-2021-0026759, Feb. 26, 2021. (Domestic, Filed)

J. Choi, T. Seong, Y. Lee, C. Hwang and H. Park, Code generation method to prevent fractional-spur generation by non-linearity of digital-to-time converter in fractional-N PLL, Application No.: 17159197, Jan. 27, 2021. (U.S., Filed)

J. Choi, T. Seong, Y. Lee, C. Hwang and H. Park, Code generation method to prevent fractional-spur generation by non-linearity of digital-to-time converter in fractional-N PLL, Application No.: 10-2020-0084110, Jul. 8, 2020. (Domestic, Filed)