Publications
J. Seo=, Y. Cho=, Y. Shin and J. Choi*, "An 850μW, 2-to-5GHz Jitter-Filtering and Instant-Toggling Injection-Locked Quadrature-Clock Generator for Low-Power Clock Distribution in HBM Interfaces," IEEE International Solid-State Circuits Conference (ISSCC), Accepted. (= Equally-Credited Authors)

Y. Cho, J. Lee, S. Park, S. Yoo, and J. Choi*, "A 12.24-GHz MDLL with a 102-Multiplication Factor Using a Power-Gating-Based Ring-Oscillator," IEEE J. Solid-State Circuits (JSSC), accepted for publication.

Y. Cho=, J. Lee=, S. Park, S. Yoo, and J. Choi, "A 122fsrms-Jitter and -60dBc-Reference-Spur 12.24GHz MDLL with a 102-Multiplication Factor Using a Power-Gating Technique," IEEE Symp. VLSI Circuits Dig., Jun. 2023. (= Equally-Credited Authors)

J. Lee=, Y. Cho=, J. Kim*, and J. Choi*, "A 0.009mm2, 6.5mW, 6.2b-ENOB 2.5GS/s Flash-and-VCO-Based Subranging ADC Using a Resistor-Ladder-Based Residue Shifter," IEEE Custom Integrated Circuits Conference (CICC), Apr. 2023. (= Equally-Credited Authors)

S. Yoo=, S. Park=, S. Choi=, Y. Cho, H. Yoon, C. Hwang, J. Choi*, "An 82fsRMS-Jitter and 22.5mW-Power, 102GHz W-Band PLL Using a Power-Gating Injection-Locked Frequency Multiplier-Based Phase Detector in 65nm CMOS," IEEE International Solid-State Circuits Conference (ISSCC), Feb. 2021. (= Equally-Credited Authors)

J. Kim, Y. Lim, H. Yoon, Y. Lee, H. Park, Y. Cho, T. Seong, and J. Choi*, "An Ultra-Low-Jitter, mmW-Band Frequency Synthesizer Based on Digital Subsampling PLL Using Optimally-Spaced Voltage Comparators," IEEE Journal of Solid-State Circuits, accepted for publication.

J. Kim**, H. Yoon**, Y. Lim**, Y. Lee, Y. Cho, T. Seong, and J. Choi*, "A 76fsrms Jitter and −40dBc Integrated-Phase-Noise 28-to-31GHz Frequency Synthesizer Based on Digital Sub-Sampling PLL Using Optimally Spaced Voltage Comparators and Background Loop-Gain Optimization," IEEE International Solid-State Circuits Conference (ISSCC), Feb. 2019. (** Equally-Credited Authors)

J. Lee, S. Choi, Y. Cho, and J. Choi*, "A linearly frequency-tunable and low-phase noise ring VCO using varactors with optimally-spaced bias voltages," Electronics Letters, Mar. 2018.

   Patents
J. Choi, J. Lee, Y. Cho, "TIME DOMAIN ANALOG TO DIGITAL CONVERTER" (​Application Num.: 10-2023-0135986)

   Awards and Honors

24th Korea Semiconductor Design Competition, Minister Award (3rd place), 2023.11.7
2023 IDEC Congress Chip Design Contest, Best Poster Award, 2023.10.26
2023 IEIE Summer Annual Conference, Best Paper Award (1st place), 2023.06.29
22nd Korea Semiconductor Design Competition, Presidential Award (1st place), 2021.10.26