Publication 

M. Chae=, S. Jang=, C. Hwang, H. Park, and J. Choi*, "A 65fsrms-Jitter and −272dB-FoMjitter,N 10.1GHz Fractional-N Digital PLL with a Quantization-Error-Compensating BBPD and an Orthogonal-Polynomial LMS Calibration," IEEE International Solid-State Circuits Conference (ISSCC), Accepted. (= Equally-Credited Authors)​​​​

S. Jang=, M. Chae=, H. Park, C. Hwang, and J. Choi*, "A Low-Jitter and Compact-Area Fractional-N Digital PLL with Fast Multi-Variable Calibration Using the Recursive Least Squares Algorithm," IEEE J. Solid-State Circuits (JSSC), Dec. 2024. (= Equally-Credited Authors)

S. Jang=, M. Chae=, H. Park=, C. Hwang, and J. Choi*, "A 5.5μs-Calibration-Time, Low-Jitter and Compact-Area Fractional-N Digital PLL Using the Recursive Least Squares (RLS) Algorithm," IEEE International Solid-State Circuits Conference (ISSCC), Feb. 2024. 

Y. Jo, J. Kim, Y. Shin, H. Park, C. Hwang, Y. Lim, and J. Choi*, "A Wideband LO Generator for 5G FR1 Bands Using a Single LC-VCO-Based Subsampling PLL and a Ring-VCO-Based Fractional-Resolution Frequency Multiplier," IEEE J. Solid-State Circuits (JSSC), Early Access.

J. Kim, Y. Jo, T. Seong, H. Park, Y. Lim*, J. Choi*, "A 12.8–15.0-GHz Low-Jitter Fractional-N Subsampling PLL Using a Voltage-Domain Quantization-Error Cancellation," IEEE J. Solid-State Circuits (JSSC), Early Access.

Y. Jo=, J. Kim=, Y. Shin, C. Hwang, H. Park, and J. Choi*, "A 135fsrms-Jitter 0.6−7.7GHz LO Generator Using a Single LC-VCO-Based Subsampling PLL and a Ring-Oscillator-Based Sub-Integer-N Frequency Multiplier", IEEE International Solid-State Circuits Conference (ISSCC), Feb. 2023. (= Equally-Credited Authors)

H. Park=, C. Hwang=, T. Seong, J. Choi*, "A Low-Jitter Ring-DCO-Based Fractional-N Digital PLL with a 1/8 DTC-Range-Reduction Technique Using a Quadruple-Timing-Margin Phase Selector," IEEE J. Solid-State Circuits (JSSC), Dec. 2022. (= Equally-Credited Authors)

C. Hwang=, H. Park=, Y. Lee, T. Seong, J. Choi*, "A Low-Jitter and Low-Fractional-Spur Ring-DCO-Based Fractional-N Digital PLL Using a DTC’s Second/Third-Order Nonlinearity Cancellation and a Probability-Density-Shaping ΔΣM,"  IEEE J. Solid-State Circuits (JSSC), Sep. 2022. (= Equally-Credited Authors)

C. Hwang=, H. Park=, T. Seong, J. Choi*, "A 188fsrms-Jitter and –243dB-FoMjitter 5.2GHz-Ring-DCO-Based Fractional-N Digital PLL with a 1/8 DTC-Range Reduction Technique Using a Quadruple-Timing-Margin Phase Selector," IEEE International Solid-State Circuits Conference (ISSCC), Feb. 2022. (= Equally-Credited Authors)

J. Kim=, Y. Jo=, Y. Lim=, T. Seong, H. Park, S. Yoo, Y. Lee, S. Choi, J. Choi*, "A 104fsRMS-Jitter and −61dBc-Fractional Spur 15GHz Fractional-N Subsampling PLL Using a Voltage-Domain Quantization-Error Cancellation Technique," IEEE International Solid-State Circuits Conference (ISSCC), Feb. 2021. (= Equally-Credited Authors)

H. Park=, C. Hwang=, T. Seong=, Y. Lee, J. Choi*, "A 365fsRMS Jitter and −63dBc-Fractional Spur, 5.3GHz-Ring-DCO-Based Fractional-N DPLL Using a DTC’s Second/Third-Order Nonlinearity Cancellation and a Probability-Density-Shaping ΔΣM," IEEE International Solid-State Circuits Conference (ISSCC), Feb. 2021. (= Equally-Credited Authors)

Y. Lim=, J. Kim=, Y. Jo, J. Bang, S. Yoo, H. Park, H. Yoon and J. Choi*, "A 170MHz-Lock-In-Range and -253dB-FOMJIT, 12-14.5GHz Subsampling PLL with 150μW Frequency-Disturbance-Correcting Loop Using a Low-Power Unevenly Spaced Edge Generator," IEEE International Solid-State Circuits Conference (ISSCC), Feb. 2020. (= Equally-Credited Authors)

Y. Lee=, T. Seong=, J. Lee, C. Hwang, H. Park, and J. Choi*, "A -240dB-FOMJIT and -115dBc/Hz-100kHz-PN, 7.7GHz-Ring-DCO-Based Digital PLL Using P/I-Gain Co-Optimization and Sequence-Rearranged Optimally Spaced TDC for Flicker-Noise Reduction," IEEE International Solid-State Circuits Conference (ISSCC), Feb. 2020. (= Equally-Credited Authors)

T. Seong=, Y. Lee=, C. Hwang, J. Lee, H. Park, K. Lee, and J. Choi*, "A -58dBc-Worst Fractional Spur and -234dB-FOMJIT, 5.5GHz-Ring-DCO-Based Fractional-N DPLL Using a Time-Invariant-Probability Modulator, Generating a Nonlinearity-Robust DTC-Control Word," IEEE International Solid-State Circuits Conference (ISSCC), Feb. 2020. (= Equally-Credited Authors)

J. Kim, Y. Lim, H. Yoon, Y. Lee, H. Park, Y. Cho, T. Seong, and J. Choi*, "An Ultra-Low-Jitter, mmW-Band Frequency Synthesizer Based on Digital Subsampling PLL Using Optimally-Spaced Voltage Comparators," IEEE Journal of Solid-State Circuits, Dec. 2019, invited from IEEE 2019 International Solid-State Circuits Conference (ISSCC).

S. Park, J. Kim, C. Hwang, H. Park, S. Yoo, T. Seong, and J. Choi*, "A 0.1-1.5 GHz Wide Harmonic-Locking-Free Delay-Locked Loop Using an Exponential DAC", IEEE Microwave and Wireless Components Letters, Aug. 2019.

   Experience 

Internship at IP developemnt team, Samsung DS, Hwasung, Korea
Sep. 2022 - Dec. 2022 


   Awards 

30th Samsung Human Tech Paper Award, Bronze Prize in Circuit Design, Feb. 2024.

22nd Korea Semiconductor Design Competition, Industry Special Award, Oct. 2021

27th Samsung Human Tech Paper Award, Silver Prize in Circuit Design, Feb. 2021.


   Patents

J. Choi, H. Park, C. Hwang and T. Seong, Delta sigma modulator to prevent fractional-spur generation by loop non-linearity in fractional-N PLL, Application No.: 10-2021-0113993, Aug. 27, 2021. (Domestic, Filed)

J. Choi, Y. Lee, T. Seong, C. Hwang and H. Park, Low-flicker-noise digital phase-locked loop using a proportional- and integral-gain co-optimization, Application No.: 10-2021-0026759, Feb. 26, 2021. (Domestic, Filed)

J. Choi, T. Seong, Y. Lee, C. Hwang and H. Park, Code generation method to prevent fractional-spur generation by non-linearity of digital-to-time converter in fractional-N PLL, Application No.: 17159197, Jan. 27, 2021. (U.S., Filed)

J. Choi, T. Seong, Y. Lee, C. Hwang and H. Park, Code generation method to prevent fractional-spur generation by non-linearity of digital-to-time converter in fractional-N PLL, Application No.: 10-2020-0084110, Jul. 8, 2020. (Domestic, Filed)