Publications

Y. Cho=, J. Lee=, S. Park, S. Yoo, and J. Choi, "A 122fsrms-Jitter and -60dBc-Reference-Spur 12.24GHz MDLL with a 102-Multiplication Factor Using a Power-Gating Technique," IEEE Symp. VLSI Circuits Dig., Jun. 2023. (= Equally-Credited Authors)

J. Lee=, Y. Cho=, J. Kim*, and J. Choi*, "A 0.009mm2, 6.5mW, 6.2b-ENOB 2.5GS/s Flash-and-VCO-Based Subranging ADC Using a Resistor-Ladder-Based Residue Shifter," IEEE Custom Integrated Circuits Conference (CICC), Apr. 2023. (= Equally-Credited Authors)

S. Park, S. Yoo, Y. Shin, J. Lee, and J. Choi*, "A Sub-100 fs-Jitter 8.16-GHz Ring-Oscillator-Based Power-Gating Injection-Locked Clock Multiplier With the Multiplication Factor of 68," IEEE Journal of Solid-State Circuits, Jan. 2023.

S. Park=, S. Yoo=, Y. Shin, J. Lee, J. Choi*, "A 97fsrms-Jitter and 68-Multiplication Factor, 8.16GHz Ring-Oscillator Injection-Locked ClockMultiplier with Power-Gating Injection-Locking and Background Multi-Functional Digital Calibrator," IEEE International Solid-State Circuits Conference (ISSCC), Feb. 2022. (= Equally-Credited Authors)

J. Bang, S. Choi, S. Yoo, J. Lee, J. Kim, and J. Choi*, "A 0.0084-mV-FOM, Fast-Transient and Low-Power External-Clock-Less Digital LDO Using a Gear-Shifting Comparator for the Wide-Range Adaptive Sampling Frequency," IEEE European Solid-State Circuits Conference (ESSCIRC), Sep. 2021.

Y. Lee=, T. Seong=, J. Lee, C. Hwang, H. Park, and J. Choi*, "A -240dB-FOMJIT and -115dBc/Hz-100kHz-PN, 7.7GHz-Ring-DCO-Based Digital PLL Using ...," IEEE International Solid-State Circuits Conference (ISSCC), accepted for presentation, Feb. 2020. (= Equally-Credited Authors)

T. Seong=, Y. Lee=, C. Hwang, J. Lee, H. Park, K. Lee, and J. Choi*, "A -58dBc-Worst Fractional Spur and -234dB-FOMJIT, 5.5GHz-Ring-DCO-Based Fractional-N DPLL Using ...," IEEE International Solid-State Circuits  Conference (ISSCC), accepted for presentation, Feb. 2020. (= Equally-Credited Authors)

J. Lee, J. Bang, Y. Lim, S. Yoo, Y. Lee, T. Seong, and J. Choi*, "A Fast-Transient and High-Accuracy, Adaptive-Sampling Digital LDO Uisng a Single VCO-Based Edge-Racing Time Quantizer," IEEE Solid-State Circuits Letters (SSC-L), Oct., 2019.

J. Lee, J. Bang, Y. Lim, and J. Choi*, "A 0.5V-VIN, 0.29ps-Transient-FOM, and Sub-2mV-Accuracy Adaptive-Sampling Digital LDO Using Single-VCO-Based Edge-Racing Time Quantizer," IEEE Symp. VLSI Circuits Dig., Jun. 2019.

Y. Lim, J. Lee, S. Park, Y. Jo, and J. Choi*, "An External Capacitorless Low-Dropout Regulator with High PSR at All Frequencies from 10 kHz to 1 GHz Using an Adaptive Supply-Ripple Cancellation Technique," IEEE Journal of Solid-State Circuits, Sep. 2018.

Y. Lim, J. Lee, Y. Lee, S. Yoo, and J. Choi*, "A 320uV-Output Ripple and 90ns-Settling Time at 0.5V Supply Digital-Analog-Hybrid LDO Using Multi-Level Gate-Voltage Generator and Fast-Decision PD Detector," IEEE European Solid-State Circuits Conference (ESSCIRC), Sep. 2018.

S. Choi, S. Yoo, Y. Lee, Y. Jo, J. Lee, Y. Lim, and J. Choi*, "153 fs RMS-Integrated-Jitter and 114-Multiplication Factor PVT-Robust 22.8 GHz Ring-LC-Hybrid Injection-Locked Clock Multiplier," IEEE Symp. VLSI Circuits Dig., Jun. 2018.

J. Lee, S. Choi, Y. Cho, and J. Choi*, "A linearly frequency-tunable and low-phase noise ring VCO using varactors with optimally-spaced bias voltages," Electronics Letters, Mar. 2018.

Y. Lim, J. Lee, Y. Lee, S. Song, H. Kim, and J. Choi, "An External Capacitor-Less Ultra-Low Dropout Regulator Using a Loop-Gain Stabilizing Technique for High Power Supply Rejection over a Wide Range of Load Current," IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Nov. 2017.
 
Y. Lim, J. Lee, S. Park, and J. Choi, "An External-Capacitor-less Low-Dropout Regulator with Less than –36dB PSRR at All Frequencies from 10kHz to 1GHz Using an Adaptive Supply-Ripple Cancellation Technique to the Body-Gate," IEEE Custom Integrated Circuits Conference (CICC), May. 2017.


Presentation

J. Lee=, Y. Cho=, J. Kim, and J. Choi*, "A 0.009mm2, 6.5mW, 6.2b-ENOB 2.5GS/s Flash-and-VCO-Based Subranging ADC Using a Resistor-Ladder-Based Residue Shifter," IEEE Custom Integrated Circuits Conference (CICC), Apr. 2023. (= Equally-Credited Authors)

J. Lee, J. Bang, Y. Lim, and J. Choi*, "A 0.5V-VIN, 0.29ps-Transient-FOM, and Sub-2mV-Accuracy Adaptive-Sampling Digital LDO Using Single-VCO-Based Edge-Racing Time Quantizer," IEEE Symp. VLSI Circuits Dig., Jun. 2019.

Domestic Patents

 
J. Choi, J. Lee, Y. Cho, "TIME DOMAIN ANALOG TO DIGITAL CONVERTER" (​Application Num.: 10-2023-0135986)
 
J. Choi, J. Lee, J. Bang, Y. Lim, S. Yoo, "DIGITAL LOW DROPOUT VOLTAGE REGULATOR USING SINGLE-VCO BASED EDGE-RACING TIME QUANTIZER" (Registration Num.: 10-2396398-0000)

J. Choi, Y. Lim, J. Lee, "DIGITAL-ANALOG HYBRID LOW DROPOUT REGULATOR" (Registration Num.: 10-2055501-0000)
 
J. Choi, Y. Lim, J. Lee, "APPARATUS AND METHOD FOR LOW DROP-OUT VOLTAGE REGULATING" (Registration Num.: 10-1878091-0000)


Scholarship

Samsung Electronics (Memory Dept. in Device Solution Dept.) Ph.D Fellowship Program (2022. 09 - 2024. 02)

Global Ph.D Fellowship Program (2018.03 - 2021.02)


Awards

2023 IDEC Congress Chip Design Contest, Best Poster Award (2023.10.26)

2023 IEIE Summer Annual Conference, Best Paper Award (2023.06.29)

2022 28th Samsung Humantech Paper Award, Silver Prize in Circuit Design (2022.02)

2021 27th Samsung Humantech Paper Award, Silver Prize in Circuit Design (2021.02)

2020 26th Samsung Humantech Paper Award, Silver Prize in Circuit Design (2020.02)

2016 16th IEEE RF/Analog IC Workshop, Best Paper Award (2016.09)