Publications

Y. Shin, Y. Jo, J. Kim, J. Lee, J. Kim, and J. Choi*, "A Digital-PLL-Based Quadrature Clock Generator for a Low-Power and Jitter-Filtering-Capable Clock Distribution Scheme in High-Speed DRAM Interfaces," IEEE J. Solid-State Circuits (JSSC), accepted for publication.

Y. Shin**, J. Lee**, J. Kim**, Y. Jo, and J. Choi*, "A 76fsrms-Jitter and −65dBc-Fractional-Spur Fractional-N Sampling PLL Using a Nonlinearity-Replication Technique," IEEE International Solid-State Circuits Conference (ISSCC), Feb. 2024. (** Equally-Credited Authors) (accepted for presentation)

Y. Jo, J. Kim, Y. Shin, H. Park, C. Hwang, Y. Lim, and J. Choi*, "A Wideband LO Generator for 5G FR1 Bands Using a Single LC-VCO-Based Subsampling PLL and a Ring-VCO-Based Fractional-Resolution Frequency Multiplier," IEEE J. Solid-State Circuits (JSSC), Early Access.

J. Kim, Y. Jo, T. Seong, H. Park, Y. Lim*, J. Choi*, "A 12.8–15.0-GHz Low-Jitter Fractional-N Subsampling PLL Using a Voltage-Domain Quantization-Error Cancellation," IEEE J. Solid-State Circuits (JSSC), Early Access.

Y. Jo**, J. Kim**, Y. Shin, C. Hwang, H. Park, and J. Choi*, "A 135fsrms-Jitter 0.6−7.7GHz LO Generator Using a Single LC-VCO-Based Subsampling PLL and a Ring-Oscillator-Based Sub-Integer-N Frequency Multiplier", IEEE International Solid-State Circuits Conference (ISSCC), Feb. 2023. (** Equally-Credited Authors)

Y. Shin**, Y. Jo**, J. Kim, J. Lee, J. Kim, and J. Choi*, "A 900μW, 1–4GHz Input-Jitter-Filtering Digital-PLL-Based 25%-Duty-Cycle Quadrature-Clock Generator for Ultra-Low-Power Clock Distribution in High-Speed DRAM Interfaces", IEEE International Solid-State Circuits Conference (ISSCC), Feb. 2023. (** Equally-Credited Authors)

Y. Lim, J. Kim, Y. Jo, J. Bang, and J. Choi*, "A Wide-Lock-In-Range and Low-Jitter 12–14.5 GHz SSPLL Using a Low-Power Frequency-Disturbance-Detecting and Correcting Loop," IEEE Journal of Solid-State Circuits (JSSC), Feb. 2022.

J. Bang, S. Choi, S. Yoo, J. Lee, J. Kim, and J. Choi*, "A 0.0084-mV-FOM, Fast-Transient and Low-Power External-Clock-Less Digital LDO Using a Gear-Shifting Comparator for the Wide-Range Adaptive Sampling Frequency," IEEE European Solid-State Circuits Conference (ESSCIRC), Sep. 2021.

J. Kim**, Y. Jo**, Y. Lim**, T. Seong, H. Park, S. Yoo, Y. Lee, S. Choi, J. Choi*, "A 104fsRMS-Jitter and −61dBc-Fractional Spur 15GHz Fractional-N Subsampling PLL Using a Voltage-Domain Quantization-Error Cancellation Technique," IEEE International Solid-State Circuits Conference (ISSCC), Feb. 2021. (** Equally-Credited Authors)

Y. Lim**, J. Kim**, Y. Jo, J. Bang, S. Yoo, H. Park, H. Yoon, and J. Choi*, "A 170MHz-Lock-In-Range and -253dB-FOMJIT, 12-14.5GHz Subsampling PLL with ...," IEEE International Solid-State Circuits Conference (ISSCC), Feb. 2020. (** Equally-Credited Authors)

J. Kim, Y. Lim, H. Yoon, Y. Lee, H. Park, Y. Cho, T. Seong, and J. Choi*, "An Ultra-Low-Jitter, mmW-Band Frequency Synthesizer Based on Digital Subsampling PLL Using Optimally-Spaced Voltage Comparators," IEEE Journal of Solid-State Circuits (JSSC), Dec. 2019, invited from IEEE 2019 International Solid-State Circuits Conference (ISSCC).

S. Park, J. Kim, C. Hwang, H. Park, S. Yoo, T. Seong, and J. Choi*, "A 0.1-1.5 GHz Wide Harmonic-Locking-Free Delay-Locked Loop Using an Exponential DAC", IEEE Microwave and Wireless Components Letters, Aug. 2019.

J. Kim**, H. Yoon**, Y. Lim**, Y. Lee, Y. Cho, T. Seong, and J. Choi*, "A 76fsRMS-Jitter and −40dBc-Integrated-Phase-Noise 28−31GHz Frequency Synthesizer Based on Digital Sub-Sampling PLL Using Optimally Spaced Voltage Comparators and Background Loop-Gain Optimization," IEEE International Solid-State Circuits Conference (ISSCC), Feb. 2019. (** Equally-Credited Authors)
 
H. Yoon, J. Kim, S. Park, Y. Lim, Y. Lee, J. Bang, K. Lim, and J. Choi, "Fractional-N Frequency Synthesizer Supporting Multiple Frequency Bands for Backward-Compatible 5G," IEEE International Solid-State Circuits Conference (ISSCC), Feb. 2018.
 
S. Yoo, S. Choi, J. Kim, H. Yoon, Y. Lee, and J. Choi, "A Low-Integrated-Phase-Noise 27-30-GHz Injection-Locked Frequency Multiplier with an Ultra-Low-Power Frequency-Tracking Loop for mm-Wave-Band 5G Transceivers," IEEE Journal of Solid-State Circuits (JSSC), Feb. 2018.
 
S. Yoo, S. Choi, J. Kim, H. Yoon, Y. Lee, and J. Choi, "A PVT-Robust 29GHz Injection-Locked Frequency Multiplier with a 600µW Frequency-Tracking Loop for mm-Band 5G Transceivers," IEEE International Solid-State Circuits Conference (ISSCC), Feb. 2017.
 

Awards
2023 ISE Summer Annual Conference, Excellent Paper Award, Jul. 2023.

2023 IDEC Congress Chip Design Contest, Excellent Design Award, Jul. 2023.

SSCS Predoctoral Achievement Award Winner, Feb. 2022

22nd Korea Semiconductor Design Competition, Corporate Special Award, Oct. 2021.

KAIST-Samsung Electronics Cooperation Center, Best Paper Award, Sep. 2021

Kim Choong-Ki Award, Best Research Achievement Award, Apr. 2021.

21st Korea Semiconductor Design Competition, Corporate Special Award, Oct. 2020.

25th Samsung HumanTech Paper Award, Bronze Prize in Circuit Design, Feb. 2019.
 
24th Samsung HumanTech Paper Award, Honorable mention in Circuit Design, Feb. 2018.