Publications

J. Bang, S. Jung, J. Kim, S. Park, and J. Choi*, "A Sub-50-fs RMS jitter, 103.5-GHz Fundamental-Sampling PLL with an Extended Loop Bandwidth," IEEE Solid-State Circuits Letters (SSC-L), Aug. 2023, invited from IEEE 2023 International Solid-State Circuits Conference (ISSCC).

J. Bang, J. Kim, S. Jung, S. Park, and J. Choi*, "A 47fsrms-Jitter and 26.6mW 103.5GHz PLL with Power-Gating Injection-Locked Frequency Multiplier-Based Phase Detector and Extended Loop Bandwidth," IEEE International Solid-State Circuits Conference (ISSCC), Feb. 2023.

S. Park, S. Yoo, Y. Shin, J. Lee, and J. Choi*, "A Sub-100 fs-Jitter 8.16-GHz Ring-Oscillator-Based Power-Gating Injection-Locked Clock Multiplier With the Multiplication Factor of 68," IEEE Journal of Solid-State Circuits (JSSC), early access.

S. Park=, S. Choi=, S. Yoo*, Y. Cho, and J. Choi*, "An Ultra-Low Jitter, Low-Power, 102-GHz PLL Using a Power-Gating Injection-Locked Frequency Multiplier-Based Phase Detector," IEEE Journal of Solid-State Circuits (JSSC), Sep. 2022. (= Equally-Credited Authors)

S. Park=, S. Yoo=, Y. Shin, J. Lee, J. Choi*, "A 97fsrms-Jitter and 68-Multiplication Factor, 8.16GHz Ring-Oscillator Injection-Locked ClockMultiplier with Power-Gating Injection-Locking and Background Multi-Functional Digital Calibrator," IEEE International Solid-State Circuits Conference (ISSCC), Feb. 2022. (= Equally-Credited Authors)

S. Yoo=, S. Park=, S. Choi=, Y. Cho, H. Yoon, C. Hwang, J. Choi*, "An 82fsRMS-Jitter and 22.5mW-Power, 102GHz W-Band PLL Using a Power-Gating Injection-Locked Frequency Multiplier-Based Phase Detector in 65nm CMOS," IEEE International Solid-State Circuits Conference (ISSCC), Feb. 2021. (= Equally-Credited Authors)

S. Park, J. Kim, C. Hwang, H. Park, S. Yoo, T. Seong, and J. Choi*, "A 0.1-1.5 GHz Wide Harmonic-Locking-Free Delay-Locked Loop Using an Exponential DAC", IEEE Microwave and Wireless Components Letters (MWCL), Aug. 2019.

H. Yoon, S. Park, and J. Choi*, "A Low-Jitter Injection-Locked Multi-Frequency Generator using Digitally-Controlled Oscillators and Time-Interleaved Calibration," IEEE Journal of Solid-State Circuits (JSSC), Feb. 2019.

Y. Lim, J. Lee, S. Park, Y. Jo, and J. Choi*, "An External Capacitorless Low-Dropout Regulator with High PSR at All Frequencies from 10 kHz to 1 GHz Using an Adaptive Supply-Ripple Cancellation Technique," IEEE Journal of Solid-State Circuits (JSSC), Sep. 2018.

H. Yoon, J. Kim, S. Park, Y. Lim, Y. Lee, J. Bang, K. Lim, and J. Choi*, "A -31dBc Integrated-Phase-Noise 29GHz Fractional-N Frequency Synthesizer Supporting Multiple Frequency Bands for Backward-Compatible 5G Using a Frequency Doubler and Injection-Locked Frequency Multipliers," IEEE International Solid-State Circuits Conference (ISSCC), Feb. 2018. 

S. Park, H. Yoon, and J. Choi*, "An Ultra-Low Phase Noise All-Digital Multi-Frequency Generator Using Injection-Locked DCOs and Time-Interleaved Calibration," IEEE Asian Solid-State Circuits Conference (ASSCC), Nov. 2017.
 
Y. Lim, J. Lee, S. Park, and J. Choi*, "An External-Capacitor-less Low-Dropout Regulator with Less than –36dB PSRR at All Frequencies from 10kHz to 1GHz Using an Adaptive Supply-Ripple Cancellation Technique to the Body-Gate," IEEE Custom Integrated Circuits Conference (CICC), May 2017.

Patents
1) Patents in South Korea
J. Choi, H. Yoon, S. Park "Multi clock generator and operating method thereof" (Patent number: 1018528320000)

J. Choi, H. Yoon, S. Park, J. Kim "FREQUENCY DISCRIMINATOR BASED ON DELAY LOCKED LOOP" (Patent number: 1020565360000)

J. Choi, S. Park, S. Yoo, S. Choi, J. Bang “An Ultra-Low Jitter, Low-Power, W/D-band PLL Using a Power-Gating Injection-Locked    Frequency Multiplier-Based Phase Detector” (Application number: 10-2022-0004049)

2) Patents in U.S.
J. Choi, S. Park, S. Yoo, S. Choi, J. Bang “ULTRA-LOW JITTER LOW-POWER W/D-BAND PHASE-LOCKED LOOP USING POWER-GATING INJECTION-LOCKED FREQUENCY MULTIPLIER BASED PHASE DETECTOR” (Application number: 17/720,257)

Awards
SSCS Predoctoral Achievement Award Winner, Feb. 2023

2022 ISOCC Chip Design Contest, Best Design Award, 2022.10.21

KAIST-Samsung Electronics Cooperation Center, Best Paper Award, Sep. 2022.

28th Samsung Humantech Paper Award, Silver Award in Circuit Design, Feb. 2022.

22nd Korea Semiconductor Design Competition, Presidential Award, 2021.10.26

2021 IDEC Congress Chip Design Contest, Best Design Award, 2021.06.24

2021 IDEC Congress Chip Design Contest, Best Poster Award, 2021.06.26

24th Samsung HumanTech Paper Award, Honorable mention in Circuit Design, Feb. 2018.