Publications

S. Yoo, S. Choi, Y. Lee, T. Seong, Y. Lim and J. Choi*, "A Low-Jitter and Low-Reference-Spur Ring-VCOBased Injection-Locked Clock Multiplier Using a Triple-Point Background Calibrator," IEEE J. Solid-State Circuits, early access, pp. 1–12, May. 2020.

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S. Yoo, S. Choi, Y. Lee, T. Seong, Y. Lim and J. Choi*, "A 140fsrms-Jitter and -72dBc-Reference-Spur Ring-VCO-Based Injection-Locked Clock Multiplier Using a Background Triple-Point Frequency/Phase/Slope Calibrator," IEEE International Solid-State Circuits Conference (ISSCC), accepted for presentation, Feb. 2020.

 

Y. Lim=, J. Kim=, Y. Jo, J. Bang, S. Yoo, H. Park, H. Yoon and J. Choi*, "A 170MHz-Lock-In-Range and -253dB-FOMJIT, 12-14.5GHz Subsampling PLL with 150μW Frequency-Disturbance-Correcting Loop Using a Low-Power Unevenly Spaced Edge Generator," IEEE International Solid-State Circuits Conference (ISSCC), accepted for presentation, Feb. 2020. (= Equally-Credited Authors)

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J. Lee, J. Bang, Y. Lim, S. Yoo, Y. Lee, T. Seong, and J. Choi*, "A Fast-Transient and High-Accuracy, Adaptive-Sampling Digital LDO Uisng a Single VCO-Based Edge-Racing Time Quantizer," IEEE Solid-State Circuits Letters (SSC-L), vol. 2, no. 12, pp. 305–308, Dec. 2019.

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T. Seong, Y. Lee, S. Yoo, and J. Choi, "A 320-fs RMS-Jitter and −75-dBc Reference-Spur Ring-DCO-Based Digital PLL Using an Optimal-Threshold TDC," IEEE J. Solid-State Circuits, vol. 54, no. 9, pp. 2501–2511, Sep. 2019.

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S. Park, J. Kim, C. Hwang, H. Park, S. Yoo, T. Seong, and J. Choi, "A 0.1-1.5 GHz Wide Harmonic-Locking-Free Delay-Locked Loop Using an Exponential DAC", IEEE Microwave and Wireless Components Letters (IEEE MWCL), vol.29, no. 8, pp. 548-550, Aug. 2019.

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S. Choi, S. Yoo, Y. Lee, Y. Jo, J. Lee, Y. Lim, and J. Choi, "An Ultra-Low-Jitter 22.8-GHz Ring-LC-Hybrid Injection Locked Clock Multiplier with a Multiplication Factor of 114," IEEE J. Solid-State Circuits, vol. 54, no. 4, pp. 927–936, Apr. 2019.

 

S. Yoo, S. Choi, Y. Lee, T. Seong, Y. Lim and J. Choi, "A 140fsRMS-Jitter and −72dBc-Reference-Spur Ring-VCO-Based Injection-Locked Clock Multiplier Using a Background Triple-Point Frequency/Phase/Slope Calibrator," IEEE International Solid-State Circuits Conference (ISSCC), Feb. 2019, accepted for presentation.

 

Y. Lim, J. Lee, Y. Lee, S. Yoo, and J. Choi, "A 320uV-Output Ripple and 90ns-Settling Time at 0.5V Supply Digital-Analog-Hybrid LDO Using Multi-Level Gate-Voltage Generator and Fast-Decision PD Detector," IEEE European Solid-State Circuits Conference (ESSCIRC), Sep. 2018.

 

S. Choi, S. Yoo, Y. Lee, Y. Jo, J. Lee, Y. Lim and J. Choi, "153 fsRMS-Integrated-Jitter and 114-Multiplication Factor PVT-Robust 22.8 GHz Ring-LC-Hybrid Injection-Locked Clock Multiplier," IEEE Symp. VLSI Circuits Dig., Jun. 2018, accepted for presentation

 

T. Seong, Y. Lee, S. Yoo and J. Choi, “A -242dB FOM and -75dBc-Reference-Spur Ring-DCO-Based All-Digital PLL Using a Fast Phase-Error Correction Technique and a Low-Power Optimal-Threshold TDC,” IEEE ISSCC Dig. Tech. Papers, Feb. 2018.

 

Y. Lee, T. Seong, S. Yoo and J. Choi, “A Low-Jitter and Low-Reference-Spur Ring-VCO-Based Switched-Loop Filter PLL Using a Fast Phase-Error Correction Technique,” IEEE J. Solid-State Circuits, vol. 53, no. 4, pp. 1192–1202, Apr 2018.

 

S. Yoo, S. Choi, J. Kim, H. Yoon, Y. Lee and J. Choi, “A Low-Integrated-Phase-Noise 27-30-GHz Injection-Locked Frequency Multiplier with an Ultra-Low-Power Frequency-Tracking Loop for mm-Wave-Band 5G Transceivers,” IEEE J. Solid-State Circuits, vol. 53, no. 2, pp. 375–388, Feb 2018.

 

T. Seong, Y. Lee, S. Yoo, and J. Choi, "A –242-dB FOM and –71-dBc Reference Spur Ring-VCO-based Ultra-Low-Jitter PLL," IEEE Symp. VLSI Circuits Dig., Jun. 2017.

 

S. Yoo, S. Choi, J. Kim, H. Yoon, Y. Lee, and J. Choi, "A PVT-Robust 29GHz Injection-Locked Frequency Multiplier with a 600uW Frequency-Tracking Loop for mm-Band 5G Transceivers," IEEE ISSCC Dig. Tech. Papers, Feb. 2017.

 

S. Choi, S. Yoo, Y. Lim and J. Choi, “A PVT-Robust and Low-Jitter Ring-VCO-Based Injection-Locked Clock Multiplier With a Continuous Frequency-Tracking Loop Using a Replica-Delay Cell and a Dual-Edge Phase Detector,” IEEE J. Solid-State Circuits, vol. 51, no. 8, pp. 1878–1889, Aug 2016.

 

S. Choi, S. Yoo and J. Choi, “A 185-fsrms Integrated-Jitter and -245dB FOM PVT-Robust Ring-VCO-Based Injection-Locked Clock Multiplier with a Continuous Frequency Tracking Loop Using a Replica-Delay Cell and a Dual-Edge Phase Detector,” IEEE ISSCC Dig. Tech. Papers, Feb. 2016.

 

S. Yoo, S. Choi, T. Seong and J. Choi, “An Ultra-Low Power and Compact LC-Tank-Based Frequency Tripler Using Pulsed Input Signals,” IEEE Microwave and Wireless Components Letters (IEEE MWCL), vol. 26, no.2, pp.140–142, Feb 2016.

 

S. Yoo, J. Kim and J. Choi, “A 2-8 GHz Wideband Dually Frequency-Tuned Ring-VCO with a Scalable Kvco,” IEEE Microwave and Wireless Components Letters (IEEE MWCL), vol. 23, no. 11, pp.602–604, Nov 2013.

 

Awards
 

• SSCS Predoctoral Achievement Award Winner, Feb. 2020

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• 25th Samsung HumanTech Paper Award, Silver Prize

  in Circuit Design, Feb. 2019

 

• 22nd Samsung HumanTech Paper Award, Silver Prize

  in Circuit Design, Feb. 2016

 

• 24th Samsung HumanTech Paper Award, Bronze Prize

  in Circuit Design, Feb. 2018

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• 23rd Samsung HumanTech Paper Award, Bronze Prize

  in Circuit Design, Feb. 2017

 

• 19th Korea Semiconductor Design Competition,

  반도체협회장상, Oct. 2018