Publications
J. Seo=, Y. Cho=, Y. Shin and J. Choi*, "An 850μW, 2-to-5GHz Jitter-Filtering and Instant-Toggling Injection-Locked Quadrature-Clock Generator for Low-Power Clock Distribution in HBM Interfaces," IEEE International Solid-State Circuits Conference (ISSCC), Accepted. (= Equally-Credited Authors)

Y. Shin, Y. Jo, J. Kim, J. Lee, J. Kim, and J. Choi*, "A Digital-PLL-Based Quadrature Clock Generator for a Low-Power and Jitter-Filtering-Capable Clock Distribution Scheme in High-Speed DRAM Interfaces," IEEE J. Solid-State Circuits (JSSC), Early Access.

Y. Shin=, J. Lee=, J. Kim=, Y. Jo, and J. Choi*, "A 76fsrms-Jitter and −65dBc-Fractional-Spur Fractional-N Sampling PLL Using a Nonlinearity-Replication Technique," IEEE International Solid-State Circuits Conference (ISSCC), Feb. 2024. (= Equally-Credited Authors)

Y. Jo, J. Kim, Y. Shin, H. Park, C. Hwang, Y. Lim, and J. Choi*, "A Wideband LO Generator for 5G FR1 Bands Using a Single LC-VCO-Based Subsampling PLL and a Ring-VCO-Based Fractional-Resolution Frequency Multiplier," IEEE Journal of Solid-State Circuits (JSSC), Oct. 2023.

Y. Shin=, Y. Jo=, J. Kim, J. Lee, J. Kim, and J. Choi*, "A 900μW, 1–4GHz Input-Jitter-Filtering Digital-PLL-Based 25%-Duty-Cycle Quadrature-Clock Generator for Ultra-Low-Power Clock Distribution in High-Speed DRAM Interfaces", IEEE International Solid-State Circuits Conference (ISSCC), Feb. 2023. (= Equally-Credited Authors)

Y. Jo=, J. Kim=, Y. Shin, C. Hwang, H. Park, and J. Choi*, "A 135fsrms-Jitter 0.6−7.7GHz LO Generator Using a Single LC-VCO-Based Subsampling PLL and a Ring-Oscillator-Based Sub-Integer-N Frequency Multiplier", IEEE International Solid-State Circuits Conference (ISSCC), Feb. 2023. (= Equally-Credited Authors)

S. Park, S. Yoo, Y. Shin, J. Lee, and J. Choi*, "A Sub-100 fs-Jitter 8.16-GHz Ring-Oscillator-Based Power-Gating Injection-Locked Clock Multiplier With the Multiplication Factor of 68," IEEE Journal of Solid-State Circuits (JSSC), Jan. 2023.

S. Park=, S. Yoo=, Y. Shin, J. Lee, J. Choi*, "A 97fsrms-Jitter and 68-Multiplication Factor, 8.16GHz Ring-Oscillator Injection-Locked Clock Multiplier with Power-Gating Injection-Locking and Background Multi-Functional Digital Calibrator," IEEE International Solid-State Circuits Conference (ISSCC), Feb. 2022. (= Equally-Credited Authors)

Awards

25th Korea Semiconductor Design Competition, Corporate Special Award, Oct. 2024.

30th Samsung Humantech Paper Award, Silver Award in Circuit Design, Feb. 2024.

24th Korea Semiconductor Design Competition, Minister Award, Nov. 2023.

2023 ISE Summer Annual Conference, Excellent Paper Award, Jul. 2023.

2023 IDEC Congress Chip Design Contest, Excellent Design Award, Jul. 2023.

2022 ISOCC Chip Design Contest, Best Design Award, Oct. 2022.

28th Samsung Humantech Paper Award, Silver Award in Circuit Design, Feb. 2022.

Patents

J. Choi, Y. Shin, Y. Jo and J. Kim, Clock generator and semiconductor device including the same, Application No.: 10-2022-0186648, Dec. 28, 2022. (Domestic, Filed)

J. Choi, Y. Shin, Y. Jo and J. Kim, Clock generator and semiconductor device including the same, Application No.: 18/347.920, Jul. 6, 2023. (U.S., Filed)

J. Choi, Y. Jo, J. Kim and Y. Shin, LO Generator for Wideband Frequency Band Cover for 5G Communication and its Operation Method, Application No.: 10-2023-0119112, Sep. 7, 2023. (Domestic, Filed)