Publications

       [Journal]

[13] C. Hwang=, H. Park=, Y. Lee, T. Seong, J. Choi*, "A Low-Jitter and Low-Fractional Spur Ring-DCO-Based Fractional-N Digital PLL Using a DTC’s Second/Third-Order Nonlinearity Cancellation and a Probability-Density-Shaping ΔΣM,"  IEEE Journal of Solid-State Circuits (JSSC), early access. (= Equally-Credited Authors)

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[12] S. Yoo, S. Choi, Y. Lee, T. Seong, Y. Lim and J. Choi*, "A Low-Jitter and Low-Reference-Spur Ring-VCOBased Injection-Locked Clock Multiplier Using a Triple-Point Background Calibrator," IEEE Journal of Solid-State Circuits (JSSC), early access, pp. 1–12, May. 2020.

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[11]  J. Lee, J. Bang, Y. Lim, S. Yoo, Y. Lee, T. Seong, and J. Choi*, "A Fast-Transient and High-Accuracy, Adaptive-Sampling Digital LDO Using a Single VCO-Based Edge-Racing Time Quantizer," IEEE Solid-State Circuits Letters (SSC-L), Dec. 2019.

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[10]  J. Kim, Y. Lim, H. Yoon, Y. Lee, H. Park, Y. Cho, T. Seong, and J. Choi*, "An Ultra-Low-Jitter, mmW-Band Frequency Synthesizer Based on Digital Subsampling PLL Using Optimally-Spaced Voltage Comparators," IEEE Journal of Solid-State Circuits (JSSC), Dec. 2019.

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[9]  T. Seong, Y. Lee, S. Yoo, and J. Choi*, "A 320-fs RMS-Jitter and −75-dBc Reference-Spur Ring-DCO-Based Digital PLL Using an Optimal-Threshold TDC," IEEE Journal of Solid-State Circuits (JSSC), Sep. 2019.

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[8]  S. Choi, S. Yoo, Y. Lee, Y. Jo, J. Lee, Y. Lim, and J. Choi*, "An Ultra-Low-Jitter 22.8-GHz Ring-LC-Hybrid Injection-Locked Clock Multiplier with a Multiplication Factor of 114," IEEE Journal of Solid-State Circuits (JSSC), Apr. 2019.

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[7]  Y. Lee, T. Seong, S. Yoo, and J. Choi*, "A Low-Jitter and Low-Reference-Spur Ring-VCO-Based Switched-Loop-Filter PLL Using a Fast Phase-Error Correction Technique," IEEE Journal of Solid-State Circuits (JSSC), Apr. 2018.

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[6]  S. Yoo, S. Choi, J. Kim, H. Yoon, Y. Lee, and J. Choi*, "A Low-Integrated-Phase-Noise 27-30-GHz Injection-Locked Frequency Multiplier with an Ultra-Low-Power Frequency-Tracking Loop for mm-Wave-Band 5G Transceivers," IEEE Journal of Solid-State Circuits (JSSC), Feb. 2018. 

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[5]  Y. Lim, J. Lee, Y. Lee, S. Song, H. Kim, and J. Choi*, "An External Capacitor-Less Ultra-Low Dropout Regulator Using a Loop-Gain Stabilizing Technique for High Power Supply Rejection over a Wide Range of Load Current," IEEE Transactions on Very Large Scale Integration (TVLSI) Systems, Nov. 2017.

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[4]  H. Yoon, Y. Lee, Y. Lim, G. Tak, H. Kim, Y. Ho, and J. Choi*, "A 0.56 – 2.92 GHz Wideband and Low Phase Noise Quadrature LO-Generator Using a Single LC-VCO for 2 – 4G Multi-Standard Cellular Transceivers," IEEE Journal of Solid-State Circuits (JSSC), Mar. 2016.

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[3]  Y. Lee, M. Kim, T. Seong, and J. Choi*, "A Low Phase Noise Injection-Locked Programmable Reference Clock Multiplier with a Two-Phase PVT-Calibrator for ΔΣ PLLs," IEEE Transactions on Circuits and Systems I (TCAS-I), Mar. 2015.

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[2]  T. Seong, Y. Lee, and J. Choi*, "An Ultra-Low In-Band Phase Noise Injection-Locked Frequency Multiplier Design Based on Open-Loop Frequency Calibration," IEEE Transactions on Circuits and Systems II (TCAS-II), Sep. 2014.

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[1]  H. Yoon, Y. Lee, and J. Choi*, "A Wideband Dual-Mode LC-VCO With a Switchable Gate-Biased Active Core," IEEE Transactions on Circuits and Systems II (TCAS-II), Apr. 2014.

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       [Conference]

[14] H. Park=, C. Hwang=, T. Seong=, Y. Lee, J. Choi*, "A 365fsRMS Jitter and −63dBc-Fractional Spur, 5.3GHz-Ring-DCO-Based Fractional-N DPLL Using a DTC’s Second/Third-Order Nonlinearity Cancellation and a Probability-Density-Shaping ΔΣM," IEEE International Solid-State Circuits Conference (ISSCC), Feb. 2021. (= Equally-Credited Authors)

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[13] J. Kim=, Y. Jo=, Y. Lim=, T. Seong, H. Park, S. Yoo, Y. Lee, S. Choi, J. Choi*, "A 104fsRMS-Jitter and −61dBc-Fractional Spur 15GHz Fractional-N Subsampling PLL Using a Voltage-Domain Quantization-Error Cancellation Technique," IEEE International Solid-State Circuits Conference (ISSCC), Feb. 2021. (= Equally-Credited Authors)

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[12]  Y. Lee=, T. Seong=, J. Lee, C. Hwang, H. Park, and J. Choi*, "A -240dB-FOMJIT and -115dBc/Hz-100kHz-PN, 7.7GHz-Ring-DCO-Based Digital PLL Using P/I-Gain Co-Optimization and Sequence-Rearranged Optimally Spaced TDC for Flicker-Noise Reduction," IEEE International Solid-State Circuits Conference (ISSCC), accepted for presentation, Feb. 2020. (= Equally-Credited Authors)

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[11]  T. Seong=, Y. Lee=, C. Hwang, J. Lee, H. Park, K. Lee, and J. Choi*, "A -58dBc-Worst Fractional Spur and -234dB-FOMJIT, 5.5GHz-Ring-DCO-Based Fractional-N DPLL Using a Time-Invariant-Probability Modulator, Generating a Nonlinearity-Robust DTC-Control Word," IEEE International Solid-State Circuits Conference (ISSCC), accepted for presentation, Feb. 2020. (= Equally-Credited Authors)

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[10]  S. Yoo, S. Choi, Y. Lee, T. Seong, Y. Lim and J. Choi*, "A 140fsrms-Jitter and -72dBc-Reference-Spur Ring-VCO-Based Injection-Locked Clock Multiplier Using a Background Triple-Point Frequency/Phase/Slope Calibrator," IEEE International Solid-State Circuits Conference Conference (ISSCC), Feb. 2019.

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[9]  J. Kim=, H. Yoon=, Y. Lim=, Y. Lee, Y. Cho, T. Seong, and J. Choi*, "A 76fsrms Jitter and −40dBc Integrated-Phase-Noise 28-to-31GHz Frequency Synthesizer Based on Digital Sub-Sampling PLL Using Optimally Spaced Voltage Comparators and Background Loop-Gain Optimization," IEEE International Solid-State Circuits Conference (ISSCC), Feb. 2019. (= Equally-Credited Authors)

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[8]  Y. Lim, J. Lee, Y. Lee, S. Yoo, and J. Choi*, "A 320uV-Output Ripple and 90ns-Settling Time at 0.5V Supply Digital-Analog-Hybrid LDO Using Multi-Level Gate-Voltage Generator and Fast-Decision PD Detector," IEEE European Solid-State Circuits Conference (ESSCIRC), Sep. 2018.

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[7]  S. Choi, S. Yoo, Y. Lee, Y. Jo, J. Lee, Y. Lim, and J. Choi*, "153fsRMS-Integrated-Jitter and 114-Multiplication Factor PVT-Robust 22.8GHz Ring-LC-Hybrid Injection-Locked Clock Multiplier," IEEE Symp. on VLSI Circuits (SOVC), Jun. 2018.

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[6]  H. Yoon, J. Kim, S. Park, Y. Lim, Y. Lee, J. Bang, K. Lim, and J. Choi*, "A -31dBc Integrated-Phase-Noise 29GHz Fractional-N Frequency Synthesizer Supporting Multiple Frequency Bands for Backward-Compatible 5G Using a Frequency Doubler and Injection-Locked Frequency Multipliers," IEEE International Solid-State Circuits Conference (ISSCC), Feb. 2018.

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[5]  T. Seong, Y. Lee, S. Yoo, and J. Choi*, "A -242dB FOM and -75dBc-Reference-Spur Ring-DCO based All-Digital PLL Using a Fast Phase-Error Correction Technique and a Low-Power Optimal-Threshold TDC," IEEE International Solid-State Circuits Conference (ISSCC), Feb. 2018.

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[4]  Y. Lee, T. Seong, S. Yoo, and J. Choi*, "A Switched-Loop-Filter PLL with a Fast Phase Error-Correction Technique", 2018 23rd Asia and South Pacific Design Automation Conference (ASP-DAC), Jan. 2018.

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[3]  T. Seong, Y. Lee, S. Yoo, and J. Choi*, "A –242-dB FOM and –71-dBc Reference Spur Ring-VCO-based Ultra-Low-Jitter PLL," IEEE Symp. on VLSI Circuits (SOVC), Jun. 2017.

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[2]  S. Yoo, S. Choi, J. Kim, H. Yoon, Y. Lee, and J. Choi*, "A PVT-Robust 29GHz Injection-Locked Frequency Multiplier with a 600uW Frequency-Tracking Loop for mm-Band 5G Transceivers," IEEE International Solid-State Circuits Conference (ISSCC), Feb. 2017.

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[1]  Y. Lee, H. Yoon, M. Kim, and J. Choi*, "A PVT-robust −59-dBc reference spur and 450-fsRMS jitter injection-locked clock multiplier using a voltage-domain period-calibrating loop," IEEE Symp. on VLSI Circuits (SOVC), Jun. 2016.

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      Patent

 

[3]  "Apparatus and Method for Injection Locked Clock Multiply,"  Patent No. 10-2018-0085164, 2018.

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[2]  "Frequency Dividing Circuit," Patent No. 10-2017-0014905, 2017.

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[1]  "Apparatus for PVT Variation Calibration of Ring OSC Based on Injection Locking System and the Method Thereof," Patent No. 10-2015-0031983, 2015.

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      Awards and Honors

 

[6]  26th Samsung Humantech Paper Award, Silver Prize in Circuit Design, Feb. 2020.

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[5]  25th Samsung Humantech Paper Award, Silver Prize in Circuit Design, Feb. 2019.

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[4]  25th Samsung Humantech Paper Award, Bronze Prize in Circuit Design, Feb. 2019.

 

[3]  19th Korea Semiconductor Design Competition, President of Semiconductor Association's Award, Oct. 2018.

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[2]  24th Samsung Humantech Paper Award, Bronze Prize in Circuit Design, Feb. 2018.

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[1]  23rd Samsung Humantech Paper Award, Bronze Prize in Circuit Design, Feb. 2017.