Yongwoo Jo
School of Electrical Engineering, KAIST
Ph.D., 2020 - Present
Contact Information
Email : yongwoo.jo@kaist.ac.kr
Education
Mar. 2018 - 2020
M.S. in Electrical and Computer Engineering
Ulsan National Institute of Science and Technology.
Mar. 2014 - Feb. 2018
B.S. in Electrical and Computer Engineering
Ulsan National Institute of Science and Technology.
International Conferences
Y. Shin=, J. Lee=, J. Kim=, Y. Jo, and J. Choi*, "A 76fsrms-Jitter and −65dBc-Fractional-Spur Fractional-N Sampling PLL Using a Nonlinearity-Replication Technique," IEEE International Solid-State Circuits Conference (ISSCC), Feb. 2024. (= Equally-Credited Authors) (accepted for presentation)
Y. Jo, J. Kim, Y. Shin, H. Park, C. Hwang, Y. Lim, and J. Choi*, "A Wideband LO Generator for 5G FR1 Bands Using a Single LC-VCO-Based Subsampling PLL and a Ring-VCO-Based Fractional-Resolution Frequency Multiplier," IEEE J. Solid-State Circuits (JSSC), Early Access.
J. Kim, Y. Jo, T. Seong, H. Park, Y. Lim*, J. Choi*, "A 12.8–15.0-GHz Low-Jitter Fractional-N Subsampling PLL Using a Voltage-Domain Quantization-Error Cancellation," IEEE J. Solid-State Circuits (JSSC), Early Access.
Y. Jo=, J. Kim=, Y. Shin, C. Hwang, H. Park, and J. Choi*, "A 135fsrms-Jitter 0.6−7.7GHz LO Generator Using a Single LC-VCO-Based Subsampling PLL and a Ring-Oscillator-Based Sub-Integer-N Frequency Multiplier", IEEE International Solid-State Circuits Conference (ISSCC), Feb. 2023. (= Equally-Credited Authors)
Y. Shin=, Y. Jo=, J. Kim, J. Lee, J. Kim, and J. Choi*, "A 900μW, 1–4GHz Input-Jitter-Filtering Digital-PLL-Based 25%-Duty-Cycle Quadrature-Clock Generator for Ultra-Low-Power Clock Distribution in High-Speed DRAM Interfaces", IEEE International Solid-State Circuits Conference (ISSCC), Feb. 2023. (= Equally-Credited Authors)
J. Kim=, Y. Jo=, Y. Lim=, T. Seong, H. Park, S. Yoo, Y. Lee, S. Choi, J. Choi*, "A 104fsRMS-Jitter and −61dBc-Fractional Spur 15GHz Fractional-N Subsampling PLL Using a Voltage-Domain Quantization-Error Cancellation Technique," IEEE International Solid-State Circuits Conference (ISSCC), Feb. 2021. (= Equally-Credited Authors)
Y. Lim=, J. Kim=, Y. Jo, J. Bang, S. Yoo, H. Park, H. Yoon and J. Choi*, "A 170MHz-Lock-In-Range and -253dB-FOMJIT, 12-14.5GHz Subsampling PLL with ...," IEEE International Solid-State Circuits Conference (ISSCC), accepted for presentation, Feb. 2020. (= Equally-Credited Authors)
S. Choi, S. Yoo, Y. Lee, Y. Jo, J. Lee, Y. Lim, and J. Choi, "153 fsRMS-Integrated-Jitter and 114-Multiplication Factor PVT-Robust 22.8 GHz Ring-LC-Hybrid Injection-Locked Clock Multiplier," IEEE Symposium on VLSI Circuits Dig., Jun. 2018, accepted for presentation
Journals
Y. Shin, Y. Jo, J. Kim, J. Lee, J. Kim, and J. Choi*, "A Digital-PLL-Based Quadrature Clock Generator for a Low-Power and Jitter-Filtering-Capable Clock Distribution Scheme in High-Speed DRAM Interfaces," IEEE J. Solid-State Circuits (JSSC), accepted for publication.
J. Kim, Y. Jo, T. Seong, H. Park, Y. Lim*, J. Choi*, "A 12.8–15.0-GHz Low-Jitter Fractional-N Subsampling PLL Using a Voltage-Domain Quantization-Error Cancellation," IEEE J. Solid-State Circuits (JSSC), Early Access.
Y. Lim, J. Kim, Y. Jo, J. Bang, and J. Choi*, "A Wide-Lock-In-Range and Low-Jitter 12–14.5 GHz SSPLL Using a Low-Power Frequency-Disturbance-Detecting and Correcting Loop," IEEE Journal of Solid-State Circuits, Oct. 2021
S. Choi, S. Yoo, Y. Lee, Y. Jo, J. Lee, Y. Lim, and J. Choi*, "An Ultra-Low-Jitter 22.8-GHz Ring-LC-Hybrid Injection-Locked Clock Multiplier with a Multiplication Factor of 114," IEEE Journal of Solid-State Circuits, Apr. 2018, invited from IEEE 2018 Symp. VLSI Circuits.