153 fsRMS-Integrated-Jitter and 114-Multiplication Factor PVT-Robust 22.8 GHz Ring-LC-Hybrid Injection-Locked Clock Multiplier

 

ICSL’s paper, “153 fsRMS-Integrated-Jitter and 114-Multiplication Factor PVT-Robust 22.8 GHz Ring-LC-Hybrid Injection-Locked Clock Multiplier”, has been accepted for presentation at the forth coming Symposium on VLSI Circuits 2018 which will be held in Hawaii.

 

Symposium on VLSI Circuits is recognized as the top conference on semiconductor circuits, along with ISSCC(International Solid-State Circuits Conference).

 

In this year’s work, an ultra-low-jitter ring-LC-hybrid injection-locked clock multiplier (ILCM) with a high multiplication factor of 114 is presented. The proposed ILCM had the highest output frequency with the largest multiplication factor among state-of-the-arts ILCMs. In addition, the proposed dual-purpose frequency calibrator (DPFC) that can calibrate the frequency drifts of the two VCOs, concurrently, consumes only 400μW. The prototype circuit was fabricated using a TSMC 65-nm CMOS process.

 

Authors: Seojin Choi, Seyeon Yoo, Yongsun Lee, Yongwoo Jo, Jeonghyun Lee, Younghyun Lim, and Jaehyouk Choi

 

Title: 153 fsRMS-Integrated-Jitter and 114-Multiplication Factor PVT-Robust 22.8 GHz Ring-LC-Hybrid Injection-Locked Clock Multiplier

 

Conference: 2018 IEEE Symposium on VLSI Circuits (Considered to be L1 paper)

 

Presentation date: Jun., 2018