A 140fsRMS-Jitter and -72dBc-Reference-Spur Ring-VCO-Based Injection-Locked Clock Multiplier Using a Background Triple-Point Frequency/Phase/Slope Calibrator

 

ICSL’s paper (authors: Seyeon Yoo, Seojin Choi, Yongsun Lee, Taeho Seong, Younghyun Lim, and Prof. Jaehyouk Choi) “A 140fsRMS-Jitter and -72dBc-Reference-Spur Ring-VCO-Based Injection-Locked Clock Multiplier Using a Background Triple-Point Frequency/Phase/Slope Calibrator” has been accepted for presentation at 2019 IEEE ISSCC (International Solid-State Circuits Conference) in San Francisco in coming February. ISSCC is called “the Olympic in the field of semiconductor circuit designs” and it is considered to be great honor to present a paper from academia. ICSL has become to stand on a podium four years in a row.

 

Authors: Seyeon Yoo, Seojin Choi, Yongsun Lee, Taeho Seong, Younghyun Lim, and Jaehyouk Choi

Title: A 140fsRMS-Jitter and -72dBc-Reference-Spur Ring-VCO-Based Injection-Locked Clock Multiplier Using a Background Triple-Point Frequency/Phase/Slope Calibrator

Conference: 2019 IEEE International Solid-State Circuit Conference (ISSCC)

Presentation date: February, 2019